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1 mx25u8035e datasheet mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
2 contents 1. features ............................................................................................................................................................... 4 2.general description ...................................................................................................................................... 6 table 1. additional feature comparison ...................................................................................................... 6 3.pin configurations .......................................................................................................................................... 7 4.pin description ................................................................................................................................................... 7 5.block diagram .................................................................................................................................................... 8 6.data protection ................................................................................................................................................. 9 table 2. protected area sizes .................................................................................................................... 10 table 3. 4k-bit secured otp defnition .................................................................................................... 10 7.memory organization ............................................................................................................................................ 11 table 4. memory organization (8mb) ......................................................................................................... 11 8.device operation ............................................................................................................................................. 12 8-1. quad peripheral interfa ce (qpi) read mode ............................................................................................. 13 9.command description .................................................................................................................................... 15 table 5. command set .............................................................................................................................. 15 9-1. w rite enable (wren) ................................................................................................................................ 17 9-2. w rite disable (wrdi) ................................................................................................................................. 17 9-3. read identifcation (rd id) ......................................................................................................................... 17 9-4. read status register (rdsr) ................................................................................................................... 17 table 6. status register ............................................................................................................................. 21 9-5. w rite status register (wrsr) ................................................................................................................... 22 table 7. protection modes ......................................................................................................................... 22 9-6. read da ta bytes (read) ........... ............................................................................................................... 23 9-7. read da ta bytes at higher speed (fast_read) .................................................................................... 23 9-8. 2 x i/o r ead mode (2read) ..................................................................................................................... 23 9-9. 4 x i/o r ead mode (4read) ..................................................................................................................... 24 9-10. burst read ................................................................................................................................................. 25 9-11. performance enhance mode ..................................................................................................................... 26 9-12. performance enhance mode reset (ffh) ................................................................................................. 26 9-13. sector erase (se) ...................................................................................................................................... 26 9-14. block erase (be32k) ................................................................................................................................. 27 9-15. block erase (be) ............ ............................................................................................................................ 27 9-16. chip erase (ce) ......................................................................................................................................... 27 9-17. page program (pp) ............ ........................................................................................................................ 28 9-18. 4 x i/o p age program (4pp) ...................................................................................................................... 28 9-19. deep power-down (dp ) ............................................................................................................................. 29 9-20. release from deep power-down (rdp), read electronic signature (res) ............................................. 29 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
3 9-21. read ele ctronic manufacturer id & device id (rems) ............................................................................. 30 9-22. qpi id read (qpiid) ................................................................................................................................. 30 table 8. id defnitions ............................................................................................................................... 30 9-23. enter secured otp (enso) ...................................................................................................................... 31 9-24. exit secured otp (exso) ......................................................................................................................... 31 9-25. read security register (rdscur) ........................................................................................................... 31 table 9. security register defnition .......................................................................................................... 32 9-26. w rite security register (wrscur) ........................................................................................................... 32 9-27. w rite protection selection (wpsel) .......................................................................................................... 32 9-28. single bl ock lock/unlock protection (sblk/sbulk) ............ .................................................................... 34 9-29. read blo ck lock status (rdblock) ........................................................................................................ 36 9-30. gang blo ck lock/unlock (gblk/gbulk) ............ ...................................................................................... 36 9-31. program/ erase suspend/ resume ........... ................................................................................................ 36 9-32. erase suspend .......................................................................................................................................... 36 9-33. program suspend ...................................................................................................................................... 37 9-34. write-resume ............................................................................................................................................ 37 9-35. no operation (nop) .................................................................................................................................. 38 9-36. software reset (reset-enable (rsten) and reset ( rst)) ...................................................................... 38 9-37. reset quad i/o (rstq io) ......................................................................................................................... 38 9-38. read sfdp mode (rdsfdp) ............ ........................................................................................................ 39 table 10. signature and parameter identifcation data values ................................................................. 40 table 11. parameter table (0): jedec flash parameter tables ............................................................... 41 table 12. parameter table (1): macronix flash parameter tables ............................................................ 43 10.power-on state .............................................................................................................................................. 45 11.electrical specifications ......................................................................................................................... 46 11-1. absolute maximum ratings ........... ............................................................................................................ 46 11-2. capacitance ............................................................................................................................................... 46 table 13. dc characteristics .................................................................................................................... 48 table 14. ac characteristics ..................................................................................................................... 49 12.timing analysis ................................................................................................................................................... 50 table 15. power-up timing ....................................................................................................................... 70 12-1. initial de livery state ................................................................................................................................... 70 13.operating conditions .................................................................................................................................. 71 13-1. at device power-up an d power-down ...................................................................................................... 71 14.erase and programming performance ............................................................................................... 73 15.latch-up characteristics ......................................................................................................................... 73 16.ordering information ................................................................................................................................. 74 17.part name description ................................................................................................................................ 75 18.package information ................................................................................................................................... 76 19.revision history ............................................................................................................................................ 80 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
4 8m-bit [x 1/x 2/x 4] 1.8v cmos mxsmio ? (serial multi i/o) flash memory 1. features general ? supports serial peripheral interface -- mode 0 and mode 3 ? 8m : 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two i/o read mode) structure or 2,097,152 x 4 bits (four i/ o read mode) structure ? equal sectors with 4k byte each, or equal blocks with 32k byte each or equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 1.65 to 2.0 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 1.0v to 1.4v performance ? high performance - fast read for spi mode - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 84mhz with 4 dummy cycles, equivalent to 168mhz - 4 i/o: 104mhz with 6 dummy cycles, equivalent to 416mhz - fast read for qpi mode - 4 i/o: 84mhz with 4 dummy cycles, equivalent to 336mhz - 4 i/o: 104mhz with 6 dummy cycles, equivalent to 416mhz - fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 10us (typical) - 8/16/32/64 byte w rap-around burst read mode - fast erase time: 45ms (typ.)/sector (4k-byte per sector); 250ms(typ.) /block (32k-byte per block); 500ms(typ.) / block (64k-byte per block); 5s(typ.) /chip ? low power consumption - low active read current: 20ma(max.) at 104mhz, 15ma(max.) at 84mhz - low active erase/programming current: 20ma (typ.) - standby current: 25ua (typ.) ? deep power down: 2ua(typ.) ? t ypical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instructions - additional 4k-bit secured otp for unique identifer ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector or block - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
5 ? status register feature ? command reset ? program/erase suspend ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? nc/sio3 - nc pin or serial input & output for 4 x i/o read mode ? p ackage - 8-pin sop (150mil) - 8-pin sop (200mil) - 8-land wson (6x5mm) - 8-land uson (4x4mm) - all devices are rohs compliant and halogen-free mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
6 2. general description the mx25u8035e are 8,388,608 bit serial flash memory, which is confgured as 1,048,576 x 8 internally. when it is in two or four i/o read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. mx25u8035e feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin and wp# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25u8035e mxsmio ? (serial multi i/o) provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specifed page or sector/block locations will be executed. progr am command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), block (32k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the mx25u8035e utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. table 1. additional feature comparison additional features part name protection and security read performance spi qpi flexible block protection (bp0-bp3) 4k-bit security otp 1 i/o (104 mhz) 2 i/o (84 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) mx25u8035e v v v v v v v v additional features part name identifer res (command: ab hex) rems (command: 90 hex) rdid (command: 9f hex) qpiid (command: af hex) mx25u8035e 34 (hex) c2 34 (hex) (if add=0) c2 25 34 c2 25 34 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
7 3. pin configurations 4.pin description 8-land uson (4x4mm) 8-pin sop (150mil) / 8-pin sop (200mil) symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection active low or serial data input & output (for 4xi/o read mode) nc/sio3 nc pin (not connected) or serial data input & output (for 4xi/o read mode) vcc + 1.8v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc nc/sio3 sclk si/sio0 8 7 6 5 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc nc/sio3 sclk si/sio0 8-land wson (6x5mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc nc/sio3 sclk si/sio0 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
8 5. block diagram address generator memory array y-decoder x-decoder data register sram buffer si/sio0 so/sio1 sio2 * sio3 * wp# * hold# * reset# * cs# sclk clock generator state machine mode logic sense amplifier hv generator output buffer * depends on part number options. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
9 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? power-on reset and tpuw: to avoid sudden power switch by system power supply transition, the power-on reset and tpuw (internal timer) may protect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase 32kb (be32k) command completion - block erase (be) command completion - chip erase (ce) comma nd completion - program/erase suspend - softreset command completion - w rite security register (wrscur) command completion - w rite protection selection (wpsel) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res) and softreset command. ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as "table 2. protected area sizes" , the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to "table 2. protected area sizes" . - the hardware proteced mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and status register write protect bit. - in f our i/o and qpi mode, the feature of hpm will be disabled. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
10 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to "table 3. 4k-bit secured otp defnition" . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp (enso) command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp (exso) command. - customer may lock-dow n the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to "table 9. security register defnition" for security register bit defnition and "table 3. 4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer , it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 2. protected area sizes table 3. .elw6hfxuhg273hqlwlrq status bit protect level bp3 bp2 bp1 bp0 8mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, protected block 15th) 0 0 1 0 2(2blocks, protected block 14th~15th) 0 0 1 1 3 (4blocks, protected block 12th~15th) 0 1 0 0 4 (8blocks, protected block 8th~15th) 0 1 0 1 5 (16blocks, protected all) 0 1 1 0 6 (16blocks, protected all) 0 1 1 1 7 (16blocks, protected all) 1 0 0 0 8 (16blocks, protected all) 1 0 0 1 9 (16blocks, protected all) 1 0 1 0 10 (16blocks, protected all) 1 0 1 1 11 (8blocks, protected block 0th~7th) 1 1 0 0 12 (12blocks, protected block 0th~11th) 1 1 0 1 13 (14blocks, protected block 0th~13th) 1 1 1 0 14 (15blocks, protected block 0th~14th) 1 1 1 1 15 (16blocks, protected all) address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
11 table 4. memory organization (8mb) 7.memory organization block (64kb) block (32kb) sector (4kb) address range 15 31 | 30 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 29 | 28 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 27 | 26 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 25 | 24 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 23 | 22 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 21 | 20 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 19 | 18 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 17 | 16 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 15 | 14 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 13 | 12 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 11 | 10 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 9 | 8 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 7 | 6 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 5 | 4 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 3 | 2 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 1 | 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
12 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. 3. when correct command is inputted to this device, it enters active mode and remains in active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data is shifted out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "figure 1. serial modes supported" . 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, rdsfdp, 2read, 4read, res, rems, sqiid, rdblock, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the followi ng instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, dp, enso, exso, wrscur, wpsel, sblk, sbulk, gbulk, suspend, resume, nop, rsten, rst, eqio, rstqio the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a w rite status register, program, or erase operation is in progress, access to the memory array is neglected and will not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
13 8-1. quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. enable qpi mode by issuing 35h command, the qpi mode is enable. figure 2. enable qpi sequence (command 35h) mode 3 sclk sio0 cs# mode 0 234567 35 sio[3:1] 0 1 reset qpi mode by issuing f5h command, the device is reset to 1-i/o spi mode. figure 3. reset qpi mode (command f5h) sclk sio[3:0] ce# f5 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
14 fast qpi read mode (fastrdq) to increase the code transmission speed, the device provides a "fast qpi read mode" (fastrdq). by issuing command code ebh, the fastrdq mode is enable. the number of dummy cycle increase from 4 to 6 cycles. the read cycle frequency will increase from 84mhz to 104mhz. figure 4. figure 5. fast qpi read mode (fastrdq) (command ebh) 3 edom sclk sio[3:0] cs# mode 3 a5 a4 a3 a2 a1 a0 x x mode 0 mode 0 msb data out data in eb h0 l0 h1 l1 h2 l2 h3 l3 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
15 9. command description table 5. command set command (byte) wren* (write enable) wrdi * (write disable) rdsr * (read status register) wrsr * (write status register) 4pp (quad page program) se * (sector erase) be 32k * (block erase 32kb) 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex) 52 (hex) 2nd byte values ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to write new values of the status register quad input to program the selected page to erase the selected sector to erase the selected 32k block command (byte) be * (block erase 64kb) ce * (chip erase) pp * (page program) dp * (deep power down) rdp * (release from deep power down) pgm/ers suspend * (suspends program/ erase) pgm/ers resume * (resumes program/ erase) 1st byte d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) b0 (hex) 30 (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 action to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode read commands i/o 1 1 1 2 4 4 4 4 read mode spi spi spi spi spi spi qpi qpi command (byte) read (normal read) fast read * (fast read data) rdsfdp (read sfdp) 2read (2 x i/o read command) note1 w4read 4read * (4 x i/o read command) note1 fast read * (fast read data) 4read * (4 x i/o read command) note1 clock rate (mhz) 33 104 104 84 84 104 84 104 1st byte 03 (hex) 0b (hex) 5a (hex) bb (hex) e7 (hex) eb (hex) 0b (hex) eb (hex) 2nd byte ad1(8) ad1(8) ad1(8) ad1(4) ad1(2) ad1(2) ad1(2) ad1(2) 3rd byte ad2(8) ad2(8) ad2(8) ad2(4) ad2(2) ad2(2) ad2(2) ad2(2) 4th byte ad3(8) ad3(8) ad3(8) ad3(4) ad3(2) ad3(2) ad3(2) ad3(2) 5th byte dummy(8) dummy(8) dummy(4) dummy(4) dummy(6) dummy(4) dummy(6) action n bytes read out until cs# goes high n bytes read out until cs# goes high read sfdp mode n bytes read out by 2 x i/ o until cs# goes high quad i/o read with 4 dummy cycles in 84mhz quad i/o read with 6 dummy cycles in 104mhz n bytes read out until cs# goes high quad i/o read with 6 dummy cycles in 104mhz program/erase commands mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
16 note 1: command set highlighted with (*) are supported both in spi and qpi mode. note 2: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on si/sio1 which is different from 1 x i/o condition. note 3: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 4: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. note 5: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. command (byte) rdid (read identifc- ation) res * (read electronic id) rems (read electronic manufacturer & device id) enso * (enter secured otp) exso * (exit secured otp) rdscur * (read security register) wrscur * (write security register) 1st byte 9f (hex) ab (hex) 90 (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 2nd byte x x 3rd byte x x 4th byte x add (note 2) 5th byte action outputs jedec id: 1-byte manufact-urer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id to enter the 4k-bit secured otp mode to exit the 4k- bit secured otp mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) command (byte) sblk * (single block lock sbulk * (single block unlock) rdblock * (block protect read) gblk * (gang block lock) gbulk * (gang block unlock) nop * (no operation) rsten * (reset enable) 1st byte 36 (hex) 39 (hex) 3c (hex) 7e (hex) 98 (hex) 00 (hex) 66 (hex) 2nd byte ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action individual block (64k- byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k- byte) unprotect read individual block or sector write protect status whole chip write protect whole chip unprotect command (byte) rst * (reset memory) eqio (enable quad i/o) rstqio (reset quad i/ o) qpiid (qpi id read) sbl * (set burst length) wpsel * (write protect selection) 1st byte 99 (hex) 35 (hex) f5 (hex) af (hex) c0 (hex) 68 (hex) 2nd byte value 3rd byte 4th byte action entering the qpi mode exiting the qpi mode id in qpi interface to set burst length to enter and enable individal block protect mode security/id/mode setting/reset commands mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
17 9-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. (please refer to "figure 19. write enable (wren) sequence (command 06) (spi mode)" and "figure 20. write enable (wren) sequence (command 06) (qpi mode)" ) 9-2. write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. (please refer to "figure 21. write disable (wrdi) sequence (command 04) (spi mode)" and "figure 23. write disable (wrdi) sequence (command 04) (qpi mode)" ) the wel bit is reset by following situations: - power-up - completion of w rite disable (wrdi) instruction - completion of w rite status register (wrsr) instruction - completion of page program (pp) instruction - completion of quad page program (4pp) instruction - completion of sector erase (se) instruction - completion of block erase 32kb (be32k) instruction - completion of block erase (be) instruction - completion of chip erase (ce) instruction - pgm/ers suspend 9-3. 5hdg,ghqwlfdwlrq5, the rdid instruction is to read the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 25(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as "table 8. id defnitions" the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code24-bits id data out on so to end rdid operation can drive cs# to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. 9-4. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
18 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdslock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. ( please refer to "figure 24. read status register (rdsr) sequence (command 05) (spi mode)" and "figure 25. read status register (rdsr) sequence (command 05) (qpi mode)" ) for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: figure 5. 3urjudp(udvhrlwkuhdgduudgdwd mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
19 figure 6. program/ erase fow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command rdscur command program /er ase su ccessfully yes no program /erase fail yes start regpfail/regefail =1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdslock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
20 figure 7. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel=1? no rds r command read w el=0, bp[3:0] , q e, and srwd data mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
21 table 6. status register note 1: see the "table 2. protected area sizes" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un- protected. qe bit. the quad enable (qe) bit, non-volatile bit, performs spi quad modes when it is reset to "0" (factory default) to enable wp# or is set to "1" to enable quad sio2 and sio3. qe bit is only valid for spi mode. when operate in spi mode, and quad io read is desired (for command ebh/e7h, or quad io program, 38h). wrsr command has to be set the through status register bit 6, the qe bit. then the spi quad i/o commands (ebh/e7h/38h) will be accepted by fash. if qe bit is not set, spi quad i/o commands (ebh/e7h/38h) will be invalid commands, the device will not respond to them. once qe bit is set, all spi commands are valid. 1i/o commands and 2io commands can be issued no matter qe bit is "0" or "1". when in qpi mode, qe bit will not affect the operation of qpi mode at all. therefore either "0" or "1" value of qe bit does not affect the qpi mode operation. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
22 9-5. write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in "table 2. protected area sizes" ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/ sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. (please refer to "figure 26. write status register (wrsr) sequence (command 01) (spi mode)" and "figure 28. write status register (wrsr) sequence (command 01) (qpi mode)" ) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 7. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in "table 2. protected area sizes" . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
23 hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system enter qpi or set qe=1, the feature of hpm will be disabled. 9-6. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. (please refer to "figure 27. read data bytes (read) sequence (command 03) (spi mode only) (33mhz)" ) 9-7. 5hdgdwdwhvdwljkhu6shhg)67b5( the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. read on spi mode the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_ read operation can use cs# to high at any time during data out. (please refer to "figure 29. read at higher speed (fast_read) sequence (command 0b) (spi mode) (104mhz)" ) read on qpi mode the sequence of issuing fast_read instruction in qpi mode is: cs# goes low sending fast_read instruction, 2 cycles 24-bit address interleave on sio3, sio2, sio1 & sio04 dummy cyclesdata out interleave on sio3, sio2, sio1 & sio0 to end qpi fast_read operation can use cs# to high at any time during data out. (please refer to "figure 30. read at higher speed (fast_read) sequence (command 0b) (qpi mode) (84mhz)" ) in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. 9-8. 2 x i/o read mode (2read) mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
24 the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address interleave on sio1 & sio0 4 dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (please refer to "figure 31. 2 x i/o read mode sequence (command bb) (spi mode only) (84mhz)" ). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. 9-9. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. (please refer to )ljxuh[,25hdg0rgh6htxhqfh&rppdqg(63,0rgh0] ). w4read instruction (e7) is also available is spi mode for 4 i/o read. the sequence is similar to 4read, but with only 4 dummy cycles. the clock rate runs at 84mhz. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the sequence of issuing 4read instruction qpi mode is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. another sequence of issuing 4 read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit random access address (please refer to )ljxuh[,25hdghqkdqfhshuirupdqfh0rgh6htxhqfh&rppdqg (63,0rgh0] and )ljxuh[,25hdghqkdqfhshuirupdqfh0rgh6htxhqfh&rppdqg(43, 0rgh0] ). in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
25 9-10. burst read this device supports burst read in both spi and qpi mode. to set the burst length, following command operation is required issuing command: c0h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. next 4 clocks is to defne wrap around depth. defnition as following table: the wrap around unit is defned within the 256byte page, with random initial address. its defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. qpi 0bh ebh and spi ebh e7h support wrap around feature after wrap around enable. burst read is supported in both spi and qpi mode. the device id default without burst read. data wrap around wrap depth data wrap around wrap depth 1xh no x 00h yes 8-byte 1xh no x 01h yes 16-byte 1xh no x 02h yes 32-byte 1xh no x 03h yes 64-byte 0 cs# sclk sio 1 1 0 0 0 0 0 0 h h h h l l l l 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 spi mode qpi mode 0 cs# sclk sio[3:0] h0 msb lsb l0 c1 c0 1 2 3 note: msb=most signifcant bit lsb=least signifcant bit mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
26 9-11. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. (please note "figure 33. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) (104mhz)" and "figure 35. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) (104mhz)" . 4xi/o read enhance performance mode sequence) performance enhance mode is supported in both spi and qpi mode. in qpi mode, ebh 0bh and spi ebh e7h commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following csb go high, the device will stay in the read mode and treat csb go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh command to exit enhance mode. 9-12. performance enhance mode reset (ffh) to conduct the performance enhance mode reset operation in spi mode, ffh command code, 8 clocks, should be issued in 1i/o sequence. in qpi mode, ffffffffh command code, 8 clocks, in 4i/o should be issued. (please refer to "figure 58. performance enhance mode reset for fast read quad i/o (spi and qpi mode)" ) if the system controller is being reset during operation, the fash device will return to the standard spi operation. upon reset of main chip, spi instruction would be issued from the system. instructions like read id (9fh) or fast read (0bh) would be issued. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to "figure 58. performance enhance mode reset for fast read quad i/o (spi and qpi mode)" ) 9-13. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization (8mb)" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to "figure 38. sector erase (se) sequence (command 20) (spi mode)" and "figure 40. sector erase (se) sequence (command 20) (qpi mode)" ) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
27 tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the sector. 9-14. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see "table 4. memory organization (8mb)" ) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte address on sics# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to "figure 39. block erase 32kb (be32k) sequence (command 52) (spi mode)" and "figure 41. block erase 32kb (be32k) sequence (command 52) (qpi mode)" ) the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the tbe32k timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (tbe32k) instruction will not be executed on the block. 9-15. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block ( please refer to "table 4. memory organization (8mb)" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to "figure 42. block erase (be) sequence (command d8) (spi mode)" and "figure 43. block erase (be) sequence (command d8) (qpi mode)" ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the block. 9-16. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
28 the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to "figure 44. chip erase (ce) sequence (command 60 or c7) (spi mode)" and "figure 45. chip erase (ce) sequence (command 60 or c7) (qpi mode)" ) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". 9-17. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. (please refer to "figure 34. page program (pp) sequence (command 02) (spi mode)" and "figure 37. page program (pp) sequence (command 02) (qpi mode)" ) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-18. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
29 9-19. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to )ljxuh'hhs3rhugrq'36htxhqfh&rppdqg63,0rgh and )ljxuh'hhs3rhugrq'36htxhqfh&rppdqg43,0rgh ) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id being reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. 9-20. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in "table 14. ac characteristics" . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions on next page. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sequence is shown as "figure 48. read electronic signature (res) sequence (command ab) (spi mode)" , )ljxuh5hdg(ohfwurqlf6ljqdwxuh5(66htxhqfh&rppdqg43,0rgh , )ljxuh5hohdhiurp 'hhs 3rhugrq 5'3 6htxhqfh &rppdqg 63, 0rgh and )ljxuh 5hohdh iurp 'hhs 3rhu grq5'36htxhqfh&rppdqg43,0rgh . even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power- down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
30 table 8. id defnitions command type mx25u8035e rdid (jedec id) manufacturer id memory type memory density c2 25 34 res electronic id 34 rems manufacturer id device id c2 34 9-21. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in "figure 52. read electronic manufacturer & device id (rems) sequence (command 90) (spi mode only)" . the device id values are listed in 7deoh,' 'hqlwlrq . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. 9-22. qpi id read (qpiid) user can execute this id read instruction to identify the device id and manufacturer id. the sequence of issue qpiid instruction is cs# goes lowsending qpi id instructiondata out on socs# goes high. most signifcant bit (msb) frst. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously , until the cs# goes high. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
31 9-23. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. 9-24. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-25. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please see "figure 53. read security register (rdscur) sequence (command 2b) (spi mode)" & "figure 54. read security register (rdscur) sequence (command 2b) (qpi mode)" . the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. /rfngrq 6hfxuhg 273 /'62 elw by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, main array access is not allowed. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
32 9-26. write security register (wrscur) the wrscur instruction is for setting the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the ldso bit is an otp bit. once the ldso bit is set, the value of ldso bit can not be altered any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please see "figure 55. write security register (wrscur) sequence (command 2f) (spi mode)" & "figure 56. write security register (wrscur) sequence (command 2f) (qpi mode)" . the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved erase suspend bit program suspend bit ldso (indicate if lock-down) secured otp indicator bit 0=normal wp mode 1=individual mode (default=0) 0=normal erase succeed 1=individual erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock non-volatile bit (otp) volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 9. 6hfxulw5hjlvwhuhqlwlrq 9-27. write protection selection (wpsel) when the system accepts and executes wpsel instruction, the bit 7 in security register will be set. the wren (write enable) instruction is required before issuing wpsel instruction. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block methods. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. every time after the system is powered-on, and the security register bit 7 is checked to be wpsel=1, all the blocks or sectors will be write protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instruction. program or erase functions can only be operated after the unlock instruction is conducted. once wpsel is setted, it cannot be changed. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
33 figure 8. wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wren command wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). wpsel instruction function fow is as follows: mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
34 figure 9. block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command 9-28. single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a specifed block (or sector) of memory, using a max -a16 or (a max -a12) address bits to assign a 64kbyte block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write protection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instructionsend 3 address bytes assign one block (or sector) t o be protected on si pin cs# goes high. the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. sblk/sbulk instruction function fow is as follows: mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
35 figure 10. block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes rdblock command to verify ( 3ch + 24bit address ) wip=0? unlock another block? yes no block unlock successfully no block unlock fail yes data = ff ? no yes unlock block completed? start wpsel=1? wpsel command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
36 9-29. read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block (or sector), using a max -a16 (or a max -a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3 address bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-30. gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-31. program/ erase suspend/ resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. details as follows. to enter the suspend/ resume mode: issuing b0h for suspend; 30h for resume (spi/qpi all acceptable) read security register bit2 (psb) and bit3 (esb) (please refer to "table 9. security register defnition" ) to check suspend ready information. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 62. suspend to read latency" , "figure 63. resume to read latency" and "figure 64. resume to suspend latency" . esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during erase operation esb=1, when erase operation resumes, esb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-32. erase suspend erase suspend allow the interruption of all erase operations. after erase suspend, wel bit will be clear, following commands can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 02h, 38h, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh ) note mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
37 note: the device is divided into 2 banks, each bank's density is 4mb. while conducting erase suspend in one bank, the programming operation that follows can only be conducted in the other bank and cannot be conducted in the bank executing the suspend operation. the boundaries of the banks are illustrated as below table. mx25u8035e bank (4m bit) address range 1 080000h-0fffffh 0 000000h-07ffffh after issue erase suspend command, latency time 20us is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 62. suspend to read latency" , "figure 63. resume to read latency" and "figure 64. resume to suspend latency" . esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during program operation esb=1, when erase operation resumes, esb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. when esb bit is issued, the write enable latch (wel) bit will be reset. see "figure 62. suspend to read latency" for suspend to read latency. 9-33. program suspend program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh ) after issue program suspend command, latency time 20us is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 62. suspend to read latency" , "figure 63. resume to read latency" and "figure 64. resume to suspend latency" . psb bit (program suspend bit) indicates the status of program suspend operation. when issue a suspend command during program operation psb=1, when program operation resumes, psb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-34. write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0 the operation of write-resume is as follows: cs# drives low send write resume command cycle (30h) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06" is not required to issue before resume. resume to another suspend operation requires tprs latency time. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
38 when erase suspend is being resumed, the wel bit need to be set again if user desire to conduct the program or erase operation. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. 9-35. no operation (nop) the "no operation" command is only able to terminate the reset enable (rsten) command and will not affect any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-36. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command and reset (rst) command. it returns the device to a standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. if the reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. the reset time is different depending on the last operation. longer latency time is required to recover from a program operation than from other operations. 9-37. reset quad i/o (rstqio) to reset the qpi mode, the rstqio (f5h) command is required. after the rstqio command is issued, the device returns from qpi mode (4 i/o interface in command cycles) to spi mode (1 i/o interface in command cycles). both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. note: for eqio and rstqio commands, cs# high width has to follow "write spec" tshsl for next instruction. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
39 9-38. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a standard of jedec. jesd216. v1.0. figure 11. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
40 table 10. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh sfdp table below is for mx25u8035em1i-10g, MX25U8035EM2I-10G, mx25u8035ezni-10g and mx25u8035ezui-10g mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
41 table 11. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111 b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 0b b0h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 0b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 007f ffff h (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100 b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 eb h ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 0000 b 00h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 ffh ffh sfdp table below is for mx25u8035em1i-10g, MX25U8035EM2I-10G, mx25u8035ezni-10g and mx25u8035ezui-10g mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
42 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 0000 b 00h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 ffh ffh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0100 b 04h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b feh unused 03:01 111 b (4-4-4) fast read 0=not support 1=support 04 1b unused 07:05 111 b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000 b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0100 b 44h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 010b (4-4-4) fast read opcode 4bh 31:24 ebh ebh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh sfdp table below is for mx25u8035em1i-10g, MX25U8035EM2I-10G, mx25u8035ezni-10g and mx25u8035ezui-10g mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
43 table 12. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 20h 00h 20h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 50h 16h 50h 16h h/w reset# pin 0=not support 1=support 65h:64h 00 0b f99ch h/w hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 1b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1001 1001 b (99h) program suspend/resume 0=not support 1=support 12 1b erase suspend/resume 0=not support 1=support 13 1b unused 14 1b wrap-around read mode 0=not support 1=support 15 1b wrap-around read mode opcode 66h 23:16 c0h c0h wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 64h 64h individual block lock 0=not support 1=support 6bh:68h 00 1b c8d9 h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 0011 0110 b (36h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11 b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh mx25u8035ebai-10g-sfdp_2014-04-09 sfdp table below is for mx25u8035em1i-10g, MX25U8035EM2I-10G, mx25u8035ezni-10g and mx25u8035ezui-10g mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
44 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefined area data is blank ffh for sfdp tables that are defined in parameter identifcation header. all other areas beyond defned sfdp table are reserved by macronix. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
45 10. power-on state the device is at below states when power-up: - standby mode ( please n ote it is not deep power down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level please refer to the fgure of "figure 66. power-up timing" . note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
46 notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. 11. electrical specifications 11-1. absolute maximum ratings figure 12. maximum negative overshoot waveform figure 13. maximum positive overshoot waveform rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 2.5v 0v -1.0v 20ns vcc+1.0v 2.0v 20ns symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v ta = 25c, f = 1.0 mhz 11-2. capacitance mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
47 figure 14. input test waveforms and measurement level figure 15. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
48 table 13. dc characteristics notes: 1. t ypical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 25 80 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 2 15 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 20 ma f=104mhz, (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma f=84mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 10 20 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 20 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
49 table 14. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read instructions 84 mhz fq clock frequency for 4read instructions (5) 84/104 mhz tch (1) tclh clock high time serial (fsclk) 4.5 ns 4pp and normal read (frsclk) 15 ns tcl (1) tcll clock low time serial (fsclk) 4.5 ns 4pp and normal read (frsclk) 15 ns tclch (2) clock rise time (peak to peak) 0.1 v/ns tchcl (2) clock fall time (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl tcsh cs# deselect time read 12 ns write/erase/program 30 ns tshqz (2) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 8 ns loading: 15pf 6 ns tclqx tho output hold time 1 ns twhsl write protect setup time (3) 20 ns tshwl write protect hold time (3) 100 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 10 us tres2 (2) cs# high to standby mode with electronic signature read 10 us trcr recovery time from read 20 us trcp recovery time from program 20 us trce recovery time from erase 12 ms tw write status register cycle time 40 ms tbp byte-program 10 30 us tpp page program cycle time 1.2 3 ms tse sector erase cycle time 45 200 ms tbe32 block erase (32kb) cycle time 250 1000 ms tbe block erase (64kb) cycle time 500 2000 ms tce chip erase cycle time 5 10 s tesl (6) erase suspend latency 20 us tpsl (6) program suspend latency 20 us tprs (7) latency between program resume and next suspend 0.3 100 us ters (8) latency between erase resume and next suspend 0.3 400 us temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
50 notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 4. test condition is shown as "figure 14. input test waveforms and measurement level" and "figure 15. output loading" . 5. when dummy cycle=4 (in both qpi & spi mode), clock rate=84mhz; when dummy cycle=6 (in both qpi & spi mode), clock rate=104mhz. 6. latency time is required for erase/program suspend until wip bit is "0". 7. for tprs, minimum timing must be observed before issuing the next program suspend command. however , a period equal to or longer than the typical timing is required in order for the program operation to make progress. 8. for ters, minimum timing must be observed before issuing the next erase suspend command. however, a period equal to or longer than the typical timing is required in order for the erase operation to make progress. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
51 figure 16. serial input timing 12. timing analysis figure 17. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
52 figure 18. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 19. write enable (wren) sequence (command 06) (spi mode) 21 34567 high-z 0 06h command sclk si cs# so figure 20. write enable (wren) sequence (command 06) (qpi mode) sclk sio[3:0] cs# 06h 0 1 command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
53 figure 21. write disable (wrdi) sequence (command 04) (spi mode) 21 34567 high-z 0 04h command sclk si cs# so figure 23. write disable (wrdi) sequence (command 04) (qpi mode) sclk sio[3:0] cs# 04h 0 1 command figure 22. read identifcation (rdid) sequence (command 9f) (spi mode only) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
54 figure 24. read status register (rdsr) sequence (command 05) (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h figure 25. read status register (rdsr) sequence (command 05) (qpi mode) 0 1 3 sclk si o[3:0] cs# 05h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 8 n h1 l1 sta tus byte status byte status byte status byte figure 26. write status register (wrsr) sequence (command 01) (spi mode) 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01h high-z command note : also supported in qpi mode with command and subsequent input/output in quad i/o mode. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
55 figure 27. read data bytes (read) sequence (command 03) (spi mode only) (33mhz) sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03h high-z command figure 28. write status register (wrsr) sequence (command 01) (qpi mode) sclk sio0 cs# c4, c0 sio1 c5, c1 5 4 0 1 2 3 sio2 c6, c2 6 sio3 c7, c3 command status 7 register in mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
56 figure 29. read at higher speed (fast_read) sequence (command 0b) (spi mode) (104mhz) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command figure 30. read at higher speed (fast_read) sequence (command 0b) (qpi mode) (84mhz) sclk sio(3:0) cs# a5 a4 a3 a2 a1 a0 x x mode 0 msb lsb msb lsb data out 1 data out 2 data in 0bh x x h0 l0 h1 l1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 edom 24 bit address command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
57 figure 31. 2 x i/o read mode sequence (command bb) (spi mode only) (84mhz) figure 32. 4 x i/o read mode sequence (command eb) (spi mode) (104mhz) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bbh address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 8 bit instruction 12 bit address 4 dummy cycle data output high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: 1. also supported in qpi mode with command and subsequent input/output in quad i/o mode and runs at 104mhz. 2. hi-impedance is inhibited for the two clock cycles. 3. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
58 figure 33. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) (104mhz) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output sclk si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
59 figure 35. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) (104mhz) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out data in ebh x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out msb lsb msb lsb msb lsb msb lsb 6 address cycles x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator n+1 ............. 3 edom 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 figure 34. page program (pp) sequence (command 02) (spi mode) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
60 figure 36. 4 x i/o page program (4pp) sequence (command 38) (spi mode only) 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 21 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 figure 37. page program (pp) sequence (command 02) (qpi mode) 2103 edom sclk sio[3:0] cs# mode 0 data byte 2 data in 02h a5 a4 a3 a2 a1 a0 h0 l0 h1 l1 h2 l2 h3 l3 h255 l255 data byte 1 data byte 3 data byte 4 data byte 256 24 bit address command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
61 figure 38. sector erase (se) sequence (command 20) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command figure 40. sector erase (se) sequence (command 20) (qpi mode) sclk sio[3:0] cs# 20h 2 3 5 7 10 a5 a4 msb lsb 4 a3 a2 6 a1 a0 24 bit address command figure 39. block erase 32kb (be32k) sequence (command 52) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command figure 41. block erase 32kb (be32k) sequence (command 52) (qpi mode) sclk sio[3:0] cs# 52h 2 3 5 7 10 a5 a4 msb 4 a3 a2 6 a1 a0 24 bit address command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
62 figure 42. block erase (be) sequence (command d8) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command figure 43. block erase (be) sequence (command d8) (qpi mode) sclk sio[3:0] cs# d8h 2 3 10 a5 a4 msb 4 5 a3 a2 6 7 a1 a0 24 bit address command figure 44. chip erase (ce) sequence (command 60 or c7) (spi mode) 21 34567 0 60h or c7h sclk si cs# command figure 45. chip erase (ce) sequence (command 60 or c7) (qpi mode) sclk sio[3:0] cs# 60h or c7h 0 1 command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
63 figure 46. deep power-down (dp) sequence (command b9) (spi mode) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command figure 47. deep power-down (dp) sequence (command b9) (qpi mode) sclk sio[3:0] cs# b9h 0 1 t dp deep power-down mode stand-by mode command figure 48. read electronic signature (res) sequence (command ab) (spi mode) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
64 figure 49. release from deep power-down (rdp) sequence (command ab) (spi mode) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command figure 50. read electronic signature (res) sequence (command ab) (qpi mode) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 mode 3 msb lsb data out data in h0 l0 deep power-down mode stand-by mode 0 abh 1 2 3 4 6 7 5 24 bit address command figure 51. release from deep power-down (rdp) sequence (command ab) (qpi mode) sclk sio[3:0] cs# abh 0 1 t res1 deep power-down mode stand-by mode command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
65 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) instruction is either 90(hex). figure 52. read electronic manufacturer & device id (rems) sequence (command 90) (spi mode only) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90h high-z command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
66 figure 53. read security register (rdscur) sequence (command 2b) (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out security register out high-z msb 7 6543210 msb 7 sclk si cs# so 2b figure 54. read security register (rdscur) sequence (command 2b) (qpi mode) 0 1 3 sclk si o[3:0] cs# 2b 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 8 n h1 l1 sta tus byte status byte status byte status byte mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
67 figure 55. write security register (wrscur) sequence (command 2f) (spi mode) 21 34567 0 2f command sclk si cs# figure 56. write security register (wrscur) sequence (command 2f) (qpi mode) sclk sio[3:0] cs# 2f 0 1 command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
68 figure 57. word read quad i/o instruction sequence (initial word read quad i/o instruction or previous p4=1) (spi mode only) (84mhz) 21 345678 9 10 11 12 13 14 15 instruction (e7h) mode 3 mode 16 17 4 00 18 20 21 22 23 19 sclk sio0 cs# 4 4 0 4 0 4 0 4 4 io switches from input to output 0 5 11 sio1 5 5 1 5 1 5 1 5 51 6 22 sio2 6 6 2 6 2 6 2 6 62 7 33 sio3 7 a23-16 a15-8 a7-0 dummy byte 1 byte 2 byte 3 7 3 7 3 7 3 7 73 figure 58. performance enhance mode reset for fast read quad i/o (spi and qpi mode) 21 34567 mode 3 don?t care (spi) ffffffffh (qpi) don?t care (spi) ffffffffh (qpi) don?t care (spi) ffffffffh (qpi) mode mode 3 mode sclk sio0 cs# sio1 ffh (spi) ffffffffh (qpi) sio2 sio3 mode bit reset for quad i/o mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
69 figure 59. reset sequence (spi mode) cs# sclk sio0 66h mode 3 mode 0 mode 3 mode 0 99h command command tshsl figure 61. reset sequence (qpi mode) mode 3 sclk sio[3:0] cs# mode 3 99h 66h mode 0 mode 3 mode 0 mode 0 tshsl command command figure 60. enable quad i/o sequence mode 3 0 1 sclk sio0 cs# mode 0 234567 35h sio[3:1] mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
70 figure 62. suspend to read latency figure 63. resume to read latency cs# tse/tbe/tpp resume command [30] read command figure 64. resume to suspend latency figure 65. software reset recovery cs# mode 66 99 stand-by mode trcr trcp trce trcr: 20us (recovery time from read) trcp: 20us (recovery time from program) trce: 12ms (recovery time from erase) cs# tprs / ters resume command suspend command tprs: program resume to another suspend ters: erase resume to another suspend cs# tpsl / tesl tpsl: program latency tesl: erase latency suspend command read command mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
71 figure 66. power-up timing note: vcc (max.) is 2.0v and vcc (min.) is 1.65v. 12-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. the parameters is characterized only. table 15. power-up timing symbol parameter min. max. unit tvsl (1) vcc(min) to cs# low (vcc rise time) 300 us v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
72 13. operating conditions 13-1. at device power-up and power-down ac timing illustrated in "figure 67. ac timing at device power-up" and "figure 68. power-down sequence" are iruwkhxssoyrowdjhdqgwkhfrqwuroljqdodwghylfhsrhuxsdqgsrhugrq,iwkhwlplqjlqwkhjxuhl ignored, the device will not operate correctly. 'xulqjsrhuxsdqgsrhugrq&6qhhgwriroorwkhyrowdjhdssolhgrq9&&wrnhhswkhghylfhqrwwreh hohfwhg7kh&6fdqehgulyhqorkhq9&&uhdfk9ffplqdqgdlwdshulrgriw96/ figure 67. ac timing at device power-up notes : 6dpsohgqrwwhwhg )ru &shfw&6/w6/&w'9&w&';w66/w&6w6&w&&/w&/&lqwkhjxuhsohdhuhihuwr "table 14. ac characteristics" . sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd symbol parameter notes min. max. unit w95 9&&5lvh7lph 1 20 500000 x9 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
73 figure 68. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
74 14. erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 1.8v, and checkerboard pattern. 2. under worst conditions of 85 c and 1.65v. 3. syste m-level overhead is the time required to execute the frst-bus-cycle sequence for the programming command. 4. the maximum chip programming time is evaluated under the worst conditions of 0c, vcc=1.8v, and 100k cycle with 90% confdence level. 15. latch-up characteristics parameter min. typ. max. unit write status register cycle time 40 ms sector erase cycle time (4kb) 45 200 ms block erase cycle time (32kb) 250 1000 ms block erase cycle time (64kb) 500 2000 ms chip erase cycle time 5 10 s byte program time (via page program command) 10 30 us page program time 1.2 3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time. mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
75 16. ordering information part no. clock (mhz) operating current typ. (ma) standby current typ. (ua) temperature package remark mx25u8035em1i-10g 104 45 5 -40 c~85 c 8-sop (150mil) MX25U8035EM2I-10G 104 45 5 -40 c~85 c 8-sop (200mil) mx25u8035ezui-10g 104 45 5 -40 c~85 c 8-uson (4x4mm) mx25u8035ezni-10g 104 45 5 -40 c~85 c 8-wson (6x5mm) mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
76 17. part name description mx 25 u 10 m1 i g option: g: rohs compliant and halogen-free speed: 10: 104mhz temperature range: i: industrial (-40c to 85c) package: m1: 150mil 8-sop m2: 200mil 8-sop zu: uson zn: wson density & mode: 8035e: 8mb type: u: 1.8v device: 25: serial flash 8035e mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
77 18. package information mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
78 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
79 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
80 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
81 19. revision history revision no. description page date 1.0 1. isolate mx25u8035e from mx25u8035e/1635 e/3235e datasheet nov/16/2010 1.1 1. corrected pag e program time from 0.9ms(typ.) to 1.2ms(typ.) p69 ma y/20/2011 2. modifed description for rohs compliance p70,71 1.2 1. added read sfdp (rdsfdp) mode p7,14,17, feb/10/2012 p41~46, 51 1.3 1. modifed tclqx value in ac characteristics table p51 dec/24/2012 2. content modif cation p38 1.4 1. updated param eters for dc characteristics. p4,48 nov/22/2013 2. updated erase and programming performance. p4,49,73 3. content modif cation p 18-20,68 4. modifed absolute maximum ratings table. p46 1.5 1. added a note for section 9-32 erase suspend p36,37 apr/23/2014 1.6 1. modifed power-up timing fgure and parameter p45,70 aug/01/2014 1.7 1. move parameters value to ac characteristics table p49 apr/02/2015 2. added resume to suspend latency p49 3. modifed block diagram p8 4. modifed note of sfdp table p44 5. updated suspe nd/resume parameters and descriptions p36,37,49,50,70 mx25u8035e p/n: pm1654 rev. 1.7, apr. 02, 2015
82 mx25u8035e macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2010~2015. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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